Computers have become ubiquitous tools of modern society. Most white collar works now work directly with a personal computer system. In order to increase the availability of computer resources, portable personal computer systems have been created. Portable personal computer systems operate on battery power and thus enable a user to use the portable personal computer in locations where traditional AC power is not available.
An electric battery can only store a limited amount of power. Once the available battery power is depleted, the user of the portable personal computer system must find a traditional AC power line to recharge the batteries. Thus, to extend the operational time, it is desirable to use the available battery power in the most efficient manner possible.
To conserve power, many processors implement various low power states. Thus, when a computer system senses that the computer is idle, the computer processor enters a low power state. When the processor is In a lower power state, the processor uses less energy than when the processor is in a normal active state.
If a computer system allows multiple bus masters and the processor in that computer system has an internal cache memory, then a special problem is presented when implementing a processor low power states. In a computer system with multiple bus masters, other peripherals coupled to the bus can control the bus and thus initiate bus transactions. For example, a hard disk control card may become a bus master and write information into a block of main memory. If the computer processor in the preceding example has copies of the block of main memory in the processor's internal cache, then the processor would have to invalidate such internal cache entries. Thus, a processor with an internal cache memory system must snoop bus transactions. Since the processor must snoop bus transactions, the processor cannot enter a fully suspended low power state.
It would therefore be desirable to implement a computer system that allows multiple bus masters wherein the processor has an internal cache memory and the processor can enter a low power state without snooping the bus.